Sr. Manager, ASIC Design

About the role

As a Sr. Manager, ASIC Design, you will lead a team of engineers in delivering complex ASIC designs from specification to tape-out. This role covers all aspects of front‑end ASIC design, including microarchitecture, RTL implementation, and verification of complex logic blocks. You will collaborate with PD, DFT, STA, and integration teams to ensure successful tape‑outs and partner with system teams for chip bring‑up and validation.

Base salary range: $200,000 to $230,000 per year. Eligible for discretionary bonus, equity, and full range of medical and other benefits.

Basic Qualifications:

• MS degree in EE/CS with 10+ years of relevant experience.
• Deep understanding of digital logic design and complex synchronous/asynchronous interfaces.
• Proficient in Verilog/System Verilog RTL design.
• Knowledge of synthesis and static timing analysis.
• Experience developing test benches and test cases; familiarity with UVM.
• Experience with gate‑level simulations, chip bring‑up, and validation.
• Proven track record of successful production tape‑outs.
• Hands‑on experience with STA and timing closure.
• Familiarity with DFT methodology and physical design flow.
• Experience in high‑speed Serdes design.

Preferred Qualifications:

• Expertise in scripting languages (Python, Tcl, Perl, Shell).
• Strong planning and estimation skills.
• Excellent communication and leadership abilities.
• Familiar with Ethernet (802.3) standards.

• Lead a team of engineers to deliver chips from specification through tape‑out.
• Mentor junior engineers on design methodologies, verification flows, and best practices.
• Develop and maintain detailed microarchitecture and design specifications.
• Design, implement, and debug complex logic blocks.
• Integrate and validate IPs from internal and external vendors.
• Support front‑end integration activities, including lint, CDC, synthesis, and ECO processes.
• Create functional tests and test benches; perform RTL and gate‑level verification and simulations.
• Collaborate with verification, DFT, and physical design teams to ensure successful tape‑out.
• Bring up, validate, and debug functional features on silicon.
• Work closely with software, firmware, applications, and systems teams to deliver a high‑quality product.

Credo’s mission is to transform connectivity at scale through fast, reliable, and energy‑efficient system solutions. Our high‑speed copper and optical interconnect products deliver industry‑leading power and performance up to 1.6 T to meet the expanding data infrastructure demands of AI.

Our product portfolio includes Zero Flap (ZF) Active Electrical Cables (AECs) and ZF optical transceivers, Omni Connect memory solutions, and a suite of retimers and DSPs for optical and copper Ethernet and PCIe, all leveraging the PILOT diagnostic and analytics software platform. Credo innovations enable our customers to connect the systems that connect the world.

Credo is committed to creating an inclusive environment for all employees and welcomes applicants from diverse backgrounds without regard to race, color, religion, gender, sex, sexual orientation, national origin, genetic information, age, disability, veteran status, or any other legally protected basis. If you have a disability or special need that requires accommodation to navigate our website or complete the application process, please email