Post silicon Validation engineer

Post Silicon Validation Engineer

Experience: 10+ years

Location: San Jose, CA

Key

Skills:

Post Silicon Validation, Oscilloscope, Multimeters, Analyzers, PCIe, Ethernet, Python, Perl

• Conduct initial power‑on, reset sequencing, clock bring‑up, and strap configuration for complex networking ASICs or So Cs
• E‑Validate Ethernet (e.g., 100G/400G/800G) MAC/PHY and PCIe (Gen 4/5/6) interfaces for physical layer integrity
• Develop, execute, and automate validation test plans and SDK‑driven test environments using Python & C/C++
• Root‑cause complex silicon, link training, and firmware bugs utilizing lab equipment such as oscilloscopes, logic analyzers, traffic generators, and protocol analyzers
• Perform system bring‑up with different configurations for Post Silicon Validation
• Execute test suites, analyze and debug issues, and create detailed reports

• Deep understanding of high‑speed Ser Des, bus protocols, and interconnect verification
• Hands‑on experience with lab tools like oscilloscopes, multimeters, analyzers, and rework procedures
• Experience with high‑speed I/Os such as PCIe (preferably Gen 4 and above) and Ethernet
• Preferred experience scripting with TCL, Python, Ruby or PERL
• Solid experience in leading and managing growing teams and embracing change
• Interaction with cross‑functional teams (FW/BIOS/Layout/Platform/IP Design/Silicon Design)
• Highly experienced in debugging interfaces using logic analyzers, oscilloscopes, and protocol analyzers
• Highly experienced in SoC / Platform bring‑up and debugging bring‑up failures
• B.E. /
  
  B.Tech. in Electronics & Communication Engineering