Principal Engineer - ASIC Verification

Overview

We are seeking an ASIC Verification Engineer with a solid ASIC/FPGA verification test strategy & development and debugging skills.

• Masters degree desired, Bachelor's degree in CS/EE is required.
• 10+ years of relevant experience in ASIC verification field.
• Should have worked on developing/implementing test plans at the chip-level for complex ASICs.
• Fluent in System Verilog and scripting languages such as Python or Perl.
• Must have intimate knowledge of UVM methodology.
• Knowledgeable about assertions and functional coverage
• Experience with code coverage, formal verification tools; familiarity with evolving verification methodologies.
• Very good communication skills and ability and desire to work in a geographically diverse team environment.
• Familiarity with embedded processor & bus functional protocols would be bonus
• Familiarity with external memory interface protocols would be a bonus
• Familiarity with validation experience with any emulation platforms would be a bonus

• Working as independent contributor in development and verification of the world leading SoCs based on latest technology ASICs and FPGAs
• Developing System Verilog/UVM based communication protocol components
• Working on test plan based on functional requirements as well as applicable standards requirements
• Working with experts of different areas to ensure the most competitive solutions
• Cooperating with system engineers, HW/SW development, suppliers and other relevant functions to solve technical issues
• Supporting HW/SW bring-up and debug