Technical Staff Engineer - Analog Design; SRAM Design

Job Title

Technical Staff Engineer – Analog Design (SRAM Design)

San Jose, California

• Define, estimate, develop, and optimize full custom high-speed SRAM block for speed, low power, area, and feature set.
• Estimate speed and power for various memory configurations and memory cell types.
• Define internal memory array architecture for redundancy, ECC compliance, and optimal speed with lowest power.
• Analyze projected SRAM yield per device versus redundancy requirements.
• Run experiments using memory compilers from EDA vendors for embedded memories to evaluate PPA trade-offs of device mix.
• Creation and verification of circuit schematics and functional Verilog models.
• Simulate and evaluate SRAM cell for cell stability, write and read margin, minimum cell operating and state retention supply level, and noise margin.
• Simulate and analyze critical paths and all features and functions.
• Optimize memory array and non-array logic transistor sizes and Vt selection for lowest possible dynamic and standby power.
• Develop and optimize sense amps for reliable operation, high speed, low power, and sufficient noise margin.
• Design testability circuitry and define SRAM test requirements.
• Write technical specifications and participate in formal reviews of other block specifications.
• Contribute to datasheet development through block characterization.
• Engage in design and verification of other circuit blocks outside of SRAM.
• Support verification and timing characterization teams.
• Drive and participate in silicon validation of SRAM blocks for functionality and performance.

• Bachelor's degree in Computer Engineering, Electrical Engineering, or Computer Science.
• 12+ years of experience in custom SRAM design and/or memory circuit design.
• High degree of SPICE simulation proficiency.
• Adept at leveraging full custom design EDA tool set.
• Demonstrated competency in scripting, managing simulation queues, data capture and analysis.
• Proficient in simulating and analyzing yield impact, reliability, and power.
• Ability to support layout, verification, timing characterization, and software model developers.
• Ability to develop and test Verilog simulation model and compare back to SPICE-based model.
• Excellent analytical, written, and verbal communication and documentation skills.
• Self‑motivated and proactive team player.
• Attention to detail and ability to drive tasks to completion independently in a timely manner.

• Master's degree in Computer Engineering, Electrical Engineering, or Computer Science.
• Experience in analog and full custom design.
• Experience in FPGA or ASIC development.
• Experience in functional verification and timing characterization.
• Experience in low power design including dual rail, array biasing, dynamic low‑power mode switching (sleep, power gating, column array muxing).
• Experience in OCV timing and yield variation analyses using Solido and Monte Carlo.

0% – 25% travel may be required.

10% sitting; 10% walking; 80% sitting in doors; usual business hours. Physical attributes: feeling, hearing, other, seeing, talking, works alone, works around others.

The annual base salary range is $91,000 – $232,000. The total compensation package includes competitive base pay, restricted stock units, quarterly bonus payments, health benefits beginning day one, retirement savings plans, and an industry‑leading ESPP program with a 2‑year look‑back feature.

Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.