Senior Hardware Layout Engineer

Endura Technologies is driving a new era of power delivery solutions, with a focus on designing cutting‑edge high-frequency IVR chips for next‑generation AI and data center systems.

Endura Technologies is driving a new era of power delivery solutions, with a focus on designing cutting‑edge high-frequency IVR chips for next‑generation AI and data center systems.

Hardware Layout Engineer (5–10 Years Experience)

San Jose, CA (Hybrid)

Endura Technologies is seeking a detail‑oriented Hardware Layout Engineer to join our growing team. This role is focused on schematic capture and PCB layout execution, working closely with design and hardware engineering teams to implement high‑performance solutions.

You will support the development of EVB and test boards for high‑frequency IVR chips and 48V power module PCBs for data center applications, contributing your expertise in PCB layout, high‑frequency design practices, and CAD tools, while collaborating with hardware design engineers who define system architecture and circuit design.

• Perform schematic capture and PCB layout for complex hardware and power systems
• Execute layout and optimization of testboards and EVBs for IVR chips and 48V power modules for data center applications
• Perform PCB layout for high‑frequency designs, including MHz switching power modules
• Design and implement evaluation boards (EVBs) for high‑frequency IVR (Integrated Voltage Regulator) applications, including schematic capture and PCB layout execution
• Use Cadence Allegro PCB Designer for layout execution, library development, and component management
• Maintain and manage component libraries and CAD databases
• Collaborate closely with hardware design engineers to ensure accurate implementation of schematics and design intent
• Support Signal Integrity (SI) and Power Integrity (PI) analysis activities in collaboration with design teams
• Assist with board‑level PDN (Power Distribution Network) extraction and optimization

• Bachelor’s or MSc in Electrical Engineering
• 5–10 years of experience in PCB layout and hardware implementation
• Strong hands‑on expertise with Cadence Allegro (schematic capture, PCB layout, library, and component management)
• Proven experience in high‑frequency PCB layout and power electronics
• Solid understanding of MHz switching layouts and PCB best practices
• Familiarity with Signal Integrity (SI) and Power Integrity (PI) concepts
• Experience with PDN extraction and optimization is highly desired

• Hybrid position based in San Jose, CA
• Opportunity to work on cutting‑edge AI and data center hardware technologies
• Collaborative and fast‑paced engineering environment
• TN visa and H1B transfer support available