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Senior DDR/LPDDRMemory Validation Lead
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-06-26
Listing for:
Altera
Full Time
position Listed on 2026-06-26
Job specializations:
-
Engineering
Test Engineer, Validation Engineer
Job Description & How to Apply Below
Altera in San Jose is seeking a highly skilled DDR5 / LPDDR5 Memory Validation Engineer to lead validation and debug activities for advanced memory interfaces on cutting-edge FPGA devices.
The role requires significant industry experience in memory subsystem validation and strong collaboration skills across multiple teams. The salary range is $149,100 - $215,000 USD, with additional incentive opportunities.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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