ASIC Design Verification Engineer

ASIC Design Verification Engineer

Come join us and take part in shaping Cisco's revolutionary solutions for data centers by designing some of the most complex chips being developed in the industry with the opportunity to get full exposure to all aspects of the systems and applications we build (Silicon, Hardware, Software, telemetry, security, etc). Our group offers a unique combination of a startup culture with the benefits of working for the leading networking company in the world!

As an ASIC Design Verification Engineer, you will play a critical role in developing Cisco's revolutionary data center solutions. You'll architect and develop DV infrastructure, create and execute comprehensive test plans, and ensure robust verification and coverage for complex chips. Your collaboration with designers, architects, and software teams will help guarantee seamless integration and optimal performance of Cisco's hardware platforms. You will:

• Participate in the ASIC design verification for Cisco high-end switching products.
• Perform end-to-end verification of design blocks and top-level.
• Develop simulation models, test plans, direct and random tests, code or functional coverage, multi-chip/system simulation, and performance analysis.
• Construct test benches components like scoreboard, agents, sequencers, and monitors.
• Collaborate with the hardware, software designers, and vendors.

• Bachelor's degree in electrical/computer science/computer engineering/related degree and 5+ years of related experience or Master's in electrical/computer science/computer engineering/related degree and 3+ years of related experience, or PhD in electrical/computer science/computer engineering/related degree + 0 years of related experience.
• Prior experience in System Verilog and UVM.
• Prior experience with ASIC design and verification processes, debugging, methodology, and tools.
• Prior experience in verifying blocks/clusters or full chip level for ASIC.

• Experience with Linux, C/C++, and/or Python/Perl.
• Prior experience in emulation.
• Post-silicon lab bring-up experience.
• Experience in Networking.
• Experience with Formal verification.
• Experience with AI agents (i.e Cursor, Codex, CoPilot, etc…)

At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions.

Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

The starting salary range posted for this position is $ to $ and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits. Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below.

For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.

U.S. employees are offered benefits, subject to Cisco's plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued…