ASIC Design Engineering Technical Leader

This Role Requires Being Onsite In San Jose, CA At Least 4 Days/Week

The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco's core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow.

Because full product development—from design to qualification to production—is within our team, we're able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.

• Drive the architecture and micro-architecture of high-performance ASIC subsystems for next-generation data center silicon.
• Influence system architecture and key design decisions across complex SoC subsystems.
• Work on some of the most challenging problems in high-performance silicon for hyperscale infrastructure.
• Design and implement high-frequency, high-performance RTL in Verilog / System Verilog, meeting aggressive timing, power, and area targets.
• Lead design specifications and technical reviews, ensuring architectural clarity and high-quality implementation.
• Drive technical execution across architecture, design, verification, and physical implementation teams to deliver robust silicon.
• Collaborate closely with verification and physical design teams to close functional coverage, timing, and integration challenges.
• Mentor engineers and elevate engineering rigor, design quality, and technical execution across the team.
• Lead debug and root-cause analysis across simulation, system bring-up, and post-silicon validation.

• Bachelor's degree in Electrical or Computer engineering and 8+ years of ASIC experience, or Master's degree in Electrical Engineering or Computer Engineering and 6+ years of ASIC experience, or PhD in Electrical Engineering or Computer Engineering + 3 years of ASIC experience.
• Experience in high-performance RTL design using Verilog/System Verilog.
• Experience with timing closure, power optimization, and clock gating techniques.
• Experience with ASIC development flows including simulation, synthesis, and static timing analysis.
• Strong debug, problem-solving, and cross-team collaboration skills.

• Understanding of data center networking and storage architectures, including RDMA and NVMe-over-TCP.
• Experience with ARM-based SoC architectures and protocols such as AXI, CHI, APB, and AHB, and ARM IP including CMN, GIC, and SMMU.
• Design experience with high-speed interfaces and controllers including PCIe, Ethernet MAC, DDR/LPDDR, and DMA engines.
• Experience integrating third-party IP into complex SoC environments.
• Proficiency in engineering automation and scripting (Python, Perl, TCL, shell).
• Experience with emulation, prototyping, or formal verification tools.