ASIC Design Engineer; Onsite
Job in
San Jose, Santa Clara County, California, 95112, USA
Listed on 2026-06-28
Listing for:
Cisco
Full Time
position Listed on 2026-06-28
Job specializations:
-
Engineering
Systems Engineer, Hardware Engineer, Electronics Engineer, Test Engineer
Job Description & How to Apply Below
ASIC Design Engineer
Define, design and take end to end Front-End ownership of ASIC subsystems to be deployed in a range of Cisco platforms. Contribute to a multi-disciplined engineering team to meet the power, performance, and area goals for products. Help define the process, methods, and tools for design and implementation of complex developments.
- Work on some of the most challenging problems in high-performance silicon for hyperscale infrastructure.
- Design and implement high-frequency, high-performance RTL in Verilog / System Verilog, meeting aggressive timing, power, and area targets.
- Lead design specifications and technical reviews, ensuring architectural clarity and high-quality implementation.
- Drive technical execution across architecture, design, verification, and physical implementation teams to deliver robust silicon.
- Collaborate closely with verification and physical design teams to close functional coverage, timing, and integration challenges.
- Mentor engineers and elevate engineering rigor, design quality, and technical execution across the team.
- Lead debug and root-cause analysis across simulation, system bring-up, and post-silicon validation.
- Creates re-usable code that promotes efficiencies in new ways
- Influence system architecture and key design decisions across complex ASIC subsystems.
- Bachelor's degree in Electrical or Computer Engineering and 7+ years of ASIC design experience, or Master's degree in Electrical or Computer Engineering and 4+ years of ASIC design experience.
- ASIC design experience, delivering silicon from microarchitecture, specification, and RTL coding through tape-out with multiple ASIC tape-outs at advanced technology nodes.
- Strong expertise in high-performance RTL design using Verilog/System Verilog.
- Deep understanding of timing closure, power optimization, and clock gating techniques.
- Experience with ASIC development flows including simulation, synthesis, and static timing analysis.
- Strong documentation, problem-solving, and technical communication skills.
- Experience working cross-functionally and collaborating with various technical teams.
- You are a problem solver who loves to tackle new challenges and a self-starter who is highly motivated and thrives on innovative technology.
- You are a strong communicator in a team setting, enjoy working in a dynamic team environment, and are an out-of-the-box thinker.
To View & Apply for jobs on this site that accept applications from your location or country, tap the button below to make a Search.
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).
Search for further Jobs Here:
×