Senior RTL-to-GDSII Engineer; 7nm
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-06-28
Listing for:
Cadence Design Systems
Full Time
position Listed on 2026-06-28
Job specializations:
-
Engineering
Systems Engineer, Engineering Design & Technologists
Job Description & How to Apply Below
Cadence Design Systems is looking for a Principal Product Engineer in San Jose, California. This role is crucial in bridging R&D and Application Engineering, influencing the next generation of chip design software.
The ideal candidate has a strong background in ASIC design flow, with 6+ years of experience and proficiency in EDA tools. Responsibilities include serving as the primary technical resource, executing benchmarks, and developing methodologies.
Cadence offers a competitive salary range of $136,500 to $253,500, with benefits including vacation, 401(k) matching, and stock purchase options.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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