Mechanical Design Engineer

Package Mechanical Design Engineer

Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon organization and a large campus with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide.

We are seeking a Package Mechanical Design Engineer to join the Cisco ASIC Group. In this role, you will lead mechanical and thermomechanical simulation efforts for ASICs and complex silicon/package/board assemblies, driving design decisions and ensuring product reliability for high-performance Cisco systems.

You will work across a globally distributed team and play a key role in shaping simulation methodologies, reliability strategies, and design guidelines across packaging, board-level integration, and system hardware engineering.

Your Impact

• Perform advanced finite element analysis (FEA) to evaluate thermomechanical reliability of ASIC packages and board-level assemblies, including stress, warpage, and interconnect integrity.
• Lead solder joint reliability simulations, including thermal cycling, mechanical shock, and vibration, and develop lifetime prediction models based on industry methodologies (e.g., Coffin-Manson, Darveaux).
• Model and analyze time-dependent material behavior, including creep, viscoplasticity, and fatigue, with temperature- and rate-dependent effects for solder materials and underfills.
• Drive board-level reliability (BLR) assessments, including PCB–package interactions, SMT effects, and system-level constraints.
• Correlate simulation results with reliability testing data (e.g., TCT, drop test, field returns) to improve model accuracy and predictive capability.
• Develop and automate simulation workflows using Python, Fortran, or similar tools to improve efficiency and repeatability.
• Provide design recommendations and reliability sign-off guidance to cross-functional teams, influencing package and system design decisions.
• Document methodologies, assumptions, and results clearly to support engineering reviews and product qualification.

Minimum Qualifications

• Bachelors + 7 years, or Masters + 4 years, or PhD + 1+ years in mechanical engineering or related field.
• Hands-on experience in thermomechanical simulation of semiconductor packages and board-level assemblies.
• Proven experience in solder joint reliability analysis, including fatigue and/or creep modeling.
• Strong experience with FEA tools such as ABAQUS or ANSYS, including nonlinear material modeling.
• Familiarity with CAD tools (e.g., Creo) and GD&T.
• Ability to collaborate across global teams.

Preferred Qualifications

• 5+ years in electronics packaging or board-level reliability (BLR) simulation.
• Experience with solder constitutive models (e.g., Anand, viscoplastic models) and fatigue life prediction methodologies.
• Knowledge of JEDEC/IPC reliability standards, including thermal cycling, drop, and mechanical testing.
• Experience with advanced packaging technologies (flip chip, 2.5D/3D, heterogeneous integration).
• Background in correlation between simulation and reliability test data.
• Strong scripting skills for simulation automation and data processing.