ASIC Design Engineer; Video Silicon IP - Multimedia Lab

ASIC Design Engineer (Video Silicon IP) - Multimedia Lab

Location:

San Jose

Team:
Technology

Employment Type:

Regular

Job Code: A100401

The Video Silicon IP team is building industry-leading, highly efficient, and scalable video codec hardware solutions (FPGA and ASIC) from the ground up to better serve our billions of users. We are looking for strong video codec design engineers to design hardware accelerators for advanced video encoding and processing. The successful candidate will be part of a fast-growing team that includes algorithm, architecture, software, firmware, and hardware design and verification experts with a dedication to technical excellence and a passion to build large-scale and high-performing video platforms and services.

Responsibilities:

• As an ASIC Design Engineer in this Video Silicon IP team, we work closely with architecture, algorithm and verification teams to build high performance and low power video processing IPs.
• Apply your knowledge of computer architecture and ASIC design to create ASIC design for compressing, processing still images and videos.
• Develop micro-architectures to meet stringent area, power, and performance (PPA) targets for multi-standard codec cores.
• Collaborate with algorithm teams to translate codec standard specifications and proprietary codec improvements into implementable hardware architectures.
• Design and implement RTL (System Verilog/Verilog) for video codec pipeline stages including intra/inter prediction, transform & quantization, entropy coding (CABAC/ANS), in-loop filters, and etc.
• Drive functional correctness in partnership with the verification team using directed and constrained-random UVM test benches; debug and close RTL coverage metrics.
• Understand synthesis, timing analysis, and CDC/RDC checks; work with physical design on floor plan and timing closure guidance.

Minimum Qualifications:

• M.S./Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
• 2 years of ASIC front-end design experience as a primary RTL owner.
• Proficiency in System Verilog RTL design or High level Synthesis (HLS).
• Familiarity with UVM/DPI/C++.
• Solid understanding of VLSI design concepts: pipelining, clock gating, memory architecture, bus interfaces (AXI/APB), and SV assertion basics.
• Scripting proficiency in Python for EDA flow automation.

Preferred Qualifications:

• Experience with Video Codec (H.265/HEVC, H.266/VVC, AV1, VP9, or H.264/AVC) is a big plus.
• Experience with relevant ISP or machine learning based image/video compression.
• Experience with FPGA prototyping for pre-silicon codec validation.
• Practical experience using LLMs (e.g., Git Hub Copilot, Claude, ChatGPT) to assist RTL design workflows.

Job Information

For Pay Transparency Compensation Description (Annually) The base salary range for this position in the selected city is $156000 - $316800 annually.

Compensation may vary outside of this range depending on a number of factors, including a candidate's qualifications, skills, competencies and experience, and location. Base pay is one part of the Total Package that is provided to compensate and recognize employees for their work, and this role may be eligible for additional discretionary bonuses/incentives, and restricted stock units.

Benefits may vary depending on the nature of employment and the country work location. Employees have day one access to medical, dental, and vision insurance, a 401(k) savings plan with company match, paid parental leave, short-term and long-term disability coverage, life insurance, wellbeing benefits, among others. Employees also receive 10 paid holidays per year, 10 paid sick days per year and 17 days of Paid Personal Time (prorated upon hire with increasing accruals by tenure).

The Company reserves the right to modify or change these benefits programs at any time, with or without notice.

For Los Angeles County (unincorporated) Candidates:
Qualified applicants with arrest or conviction records will be considered for employment in accordance with all federal, state, and local laws including the Los Angeles County Fair Chance Ordinance for Employers and the California Fair Chance Act.

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