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Principal Engineer, Mixed Signal Logic Design Engineer

Job in San Jose, Santa Clara County, California, 95112, USA
Listing for: Intel Corporation
Full Time position
Listed on 2026-07-01
Job specializations:
  • Engineering
    Systems Engineer
Job Description & How to Apply Below

Job Title

Principal Engineer

Job Description

Develops the logic design, register transfer level (RTL) coding, and simulation for mixed signal and/or highspeed IPs required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.

Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high quality integration of the IP block. As a principal engineer, recognized as a domain expert who influences and drives technical direction across Intel and industry. Develops and mentors other technical leaders, grows the community, acts as a change agent, and role models Intel values.

Aligns organizational goals with technical vision, formulates technical strategy to deliver leadership solutions, and demonstrates a track record of relentless execution in bringing products and technologies to market.

Qualifications

Minimum Qualifications
- Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related STEM field with 12+ years of relevant experience, OR
- Proficiency in System Verilog, including experience with OVM/UVM methodologies.

- Demonstrated experience in developing IP or SoC verification environments, writing validation plans, and executing test cases.

Preferred Qualifications
- Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related STEM field with 10+ years of relevant experience, OR
- PhD in a related STEM field with 8 years of experience.

- 3+ years of experience with DFI/DDR/LPDDR Protocols.

- Experience in DDR Phy verification or Memory Controller verification.

- Strong problem-solving skills and a proactive approach to tackling complex technical challenges.

- Ability to work collaboratively across multidisciplinary teams to achieve technical goals.

We are looking for individuals who are passionate about pushing the boundaries of technology and excited by the opportunity to make a tangible impact in a dynamic, forward-thinking team. Apply today to be part of Intel's journey to redefine the future of innovation.

Job Type

Experienced Hire

Shift

Shift 1 (United States of America)

Primary Location

US, California, Folsom

Additional Locations

US, California, San Jose

Business Group

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars:
Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Benefits

We offer a total compensation package that ranks among the best in the industry. It…

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