Lead Design Engineer – Design​/Validation, Memory Interfaces

Location | Work Mode | Experience

• Location:
  
  San Jose, CA, USA
• Work Mode:
  Full-time, Onsite
• Experience:
  
  B.Tech with 6+ years / M.Tech with 4+ years

We are looking for a Lead Design Engineer for an onsite role based in San Jose, CA
. The role focuses on leading design and validation activities for next-generation memory interface technologies, including DDR5, LPDDR5/LPDDR6, HBM4, and GDDR7
.

The engineer will drive electrical and functional validation, post-silicon bring‑up, debug, characterization, automation, and customer‑facing technical support. This role requires strong ownership, cross‑functional coordination, and hands‑on experience in semiconductor product development.

• Lead end‑to‑end design and validation activities for advanced memory interface products.
• Drive electrical and functional validation for DDR5, LPDDR5, LPDDR6, HBM4, and GDDR7 interfaces.
• Define and execute post‑silicon bring‑up and validation strategies.
• Perform silicon characterization, debug, and performance analysis.
• Develop Python‑based automation frameworks for validation, data processing, and reporting.
• Analyze complex validation datasets and convert findings into actionable engineering insights.
• Lead structured debug activities for system‑level and silicon‑level issues.
• Manage issue tracking and resolution using JIRA‑based workflows.
• Collaborate with design, validation, applications, product, and customer engineering teams.
• Prepare detailed characterization reports and technical validation summaries.
• Support customer debug, issue resolution, and technical discussions.
• Mentor junior engineers and contribute to validation process improvements.

• B.Tech with 6+ years or M.Tech with 4+ years of relevant experience.
• Degree in Electrical Engineering, Electronics, Computer Engineering, VLSI, or related field.
• Hands‑on experience in semiconductor design, validation, or post‑silicon validation.
• Strong experience with DDR memory interfaces or high‑speed interface validation.
• Experience in silicon bring‑up, electrical validation, functional validation, and debug.
• Strong Python scripting or automation experience.
• Ability to work onsite in San Jose, CA.
• Strong analytical, problem‑solving, and technical communication skills.