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Sr. Design Verification Engineer
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-07-16
Listing for:
ThinkIQ
Full Time
position Listed on 2026-07-16
Job specializations:
-
Engineering
Test Engineer, Quality Engineering, Validation Engineer
Job Description & How to Apply Below
About the role:
Ensure quality/performance of complex digital designs through rigorous verification; develop/execute plans, build reusable UVM test benches, write sequences, debug, and collaborate with RTL/fw/app engineering. Base salary range is $130,000 – $160,000 a year. Eligible for bonus, equity, and full benefits.
- Develop verification/test plans
- Build SV‑UVM environments
- Verify PCIe subsystems/interfaces
- Write assertions, checkers, and coverage
- Analyze coverage
- Run firmware‑based simulations in C
- Reproduce silicon failures
- Automate tasks with Python, Perl, and Shell
- BS/MS in EE/CE
- 7+ years experience with SV/UVM
- PCIe verification expertise
- Gate‑level and firmware‑based simulation experience
- Knowledge of RTL and computer architecture
- Strong debugging skills
- Cross‑functional collaboration experience
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