Senior Physical Design Engineer​/Lead

Altera is the world’s largest pure‑play FPGA solutions provider, focusing on innovation across AI, cloud, networking, and edge markets.

As a Physical Design Engineer Altera, you will play a critical role in the backend implementation flow – from RTL/netlist through to GDSII/tape‑out for FPGA/SoC devices. You will collaborate with architecture, logic design, DFT, CAD/EDA, and manufacturing teams to achieve our performance/power/area (PPA) goals, with emphasis on programmable logic structures, block and full‑chip integration, and the unique demands of FPGA technologies.

• Lead and execute physical design implementation tasks (floor planning, power planning, placement, clock tree synthesis (CTS), routing, engineering change orders (ECO), extraction, sign‑off preparation) from netlist to GDSII.
• Apply PPA optimization techniques across blocks or full‑chip hierarchies to achieve performance, timing closure, power reduction and area efficiency.
• Collaborate with front‑end design, architecture, CAD/EDA tool teams to enforce physical design constraints, timing budgets, power budgets, and DFT insertions.
• Develop and improve physical design flows, methodologies, scripts and automation frameworks (TCL, Python, Perl) to accelerate turnaround and reduce manual intervention.
• Participate in timing, power, EM/IR integrity, signal/power noise, DRC/LVS/ERC verification and sign‑off readiness.
• Integrate FPGA‑specific physical design aspects such as configurable logic block placement, fabric routing, I/O ring optimization, power domain regulation and yield optimization.
• Work closely with manufacturing and packaging partners to ensure implementations are manufacturable, meet yield targets and high‑volume production requirements.
• Debug physical design issues and collaborate with CAD tool vendors and internal tool teams to drive tool enhancements or workarounds.
• Mentor junior engineers and contribute to reviews, documentation and continuous process improvement.

Bay Area, California: $149,100–$215,000

USD (range may vary based on location, experience, skills and knowledge). Incentive opportunities may be available.

Minimum Qualifications:

• Bachelor’s degree in Electrical Engineering, Computer Engineering or a related discipline with 10+ years of industry experience in physical design, implementation or SoC backend design.
• 10+ years of hands‑on experience in digital ASIC and/or SoC physical design, including synthesis, floor planning, place‑and‑route, clock tree synthesis, routing, ECO implementation and sign‑off.
• 8+ years of experience using industry‑standard EDA implementation and sign‑off tools such as Synopsys IC Compiler II, Synopsys Fusion Compiler, Cadence Innovus, Cadence Encounter, Synopsys Prime Time, Synopsys StarRC, Mentor Calibre or equivalent.
• 5+ years of scripting and automation experience using Tcl for physical design flow development and automation.
• 2+ years of experience using Python, Perl, Shell or similar languages to improve productivity and workflow automation.
• 5+ years of experience implementing low‑power design methodologies including clock gating, multi‑power domain implementation, power intent and power‑aware physical design.
• 5+ years of experience performing static timing analysis and timing closure for high‑speed ASIC or SoC designs.
• 3+ years of experience performing power integrity, IR‑drop, EM, signal‑integrity analysis and recommending corrective actions.
• 5+ years of experience working with physical verification and sign‑off activities such as DRC, LVS, ERC, DFM and related manufacturing verification flows.
• 5+ years of collaboration with front‑end RTL, architecture, CAD/EDA, manufacturing, packaging and DFT teams throughout the physical implementation lifecycle.
• 3+ years of experience performing chip integration activities such as physical block integration, pin assignment, timing and constraint push‑down, and hierarchical implementation.
• 2+ years of experience with bump planning, redistribution layer routing, MiM capacitor planning, ESD sign‑off or advanced package‑aware physical implementation.
• 2+ years of experience performing I/O budgeting and implementation across…