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Senior PCIe IP Design Engineer; Gen-Gen
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-07-19
Listing for:
Sivaltech
Full Time
position Listed on 2026-07-19
Job specializations:
-
Engineering
Electronics Engineer, Hardware Engineer
Job Description & How to Apply Below
Sivaltech is seeking an experienced PCIe IP Design Engineer to join our high-performance IP development team. The candidate will design and develop PCI Express IPs, focusing on RTL design, microarchitecture, and high-speed interfaces.
The role requires hands-on PCIe IP design (Gen4/Gen5/Gen6 preferred), Verilog/System Verilog RTL coding, and a deep understanding of PCIe protocol architecture, including TL, DLL, PHY, LTSSM, and DMA concepts.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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