Physical Design Implementation and STA Lead

## Physical Design Implementation and STA Lead Apply locations:
San Jose, California, United Statestime type:
Full time posted on:
Posted Yesterday job requisition :
R02755#
** Job Details:**### ##
*
* Job Description:

**** About Altera
** At AlteraTM, our independence as the world’s largest pure‐play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‐leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.
** About the Role
** We are seeking an experienced
** Physical Design Implementation & Static Timing Analysis (STA) Lead
** to play a key technical role in delivering high-quality physical implementation and timing closure for next-generation FPGA SoCs. In this role, you will lead physical design implementation and static timing analysis activities for complex blocks and SoC subsystems, driving implementation from floor planning through final timing closure while partnering closely with RTL, architecture, DFT, CAD, and signoff teams.

This is a highly technical individual contributor role with project leadership responsibilities. You will provide technical guidance to engineers across implementation and timing closure activities while helping improve methodologies and evaluating emerging ML/AI-assisted physical design technologies.
** Key Responsibilities
**** Physical Design Implementation
*** Lead block-level physical implementation including synthesis, floor planning, place-and-route, clock tree synthesis (CTS), optimization, and ECO closure.
* Support SoC-level physical implementation and collaborate on floor planning, partitioning, and integration strategies.
* Develop and maintain implementation constraints including SDC and UPF to achieve timing, power, and area (PPA) goals.
* Partner with RTL, DFT, CAD, packaging, and library teams to resolve implementation issues throughout the design cycle.
* Drive implementation convergence across timing, power, congestion, and routability objectives.
* Contribute to methodology improvements and implementation best practices.
** Static Timing Analysis (STA)
*** Lead static timing analysis (STA) and timing closure across multiple process, voltage, and temperature corners (MMMC).
* Perform timing analysis using Synopsys Prime Time or equivalent STA tools.
* Identify and resolve setup, hold, recovery, removal, SI/crosstalk, and clock-related timing violations.
* Drive timing-driven ECO implementation in collaboration with RTL and physical design teams.
* Develop timing constraints and validate timing exceptions to ensure robust signoff quality.
* Partner with library, CAD, and methodology teams to improve timing closure efficiency.
** Signoff & Physical Verification
*** Execute signoff activities including IR drop, electromigration (EM), DRC, LVS, antenna, and physical verification.
* Analyze congestion, routing quality, clock quality, and PPA tradeoffs.
* Support implementation planning to achieve project schedules and tapeout milestones.
** Automation & ML/AI
*** Utilize ML/AI-assisted implementation technologies to improve timing closure and physical design productivity.
* Develop Tcl and Python automation to streamline implementation and timing analysis workflows.
* Collaborate with CAD teams to evaluate AI-assisted optimization methodologies and next-generation implementation flows.
* Analyze implementation metrics and timing data to identify optimization opportunities.
** Technical Leadership
*** Provide technical leadership for physical implementation and STA activities across one or more projects.
* Mentor junior and mid-level physical design engineers on implementation and timing closure methodologies.
* Participate in design reviews, timing reviews, and signoff readiness meetings.
* Contribute to reusable methodologies, automation, and engineering best practices.
**…