Senior Mixed-Signal Verification Engineer -Power Management ICs

Senior Mixed-Signal Verification Engineer - Power Management ICs

Tyl Semi, Inc. San Jose, California, United States

• Develop and execute mixed-signal verification plans for high-current IVR designs.
• Build and maintain analog behavioral models (Verilog-A / System Verilog real-number modeling) for power stages, integrated inductors, PDN, and analog blocks.
• Perform analog-digital co-simulation using industry-standard tools (Cadence Xcelium+Spectre, Synopsys VCS + Fine Sim/Custom Sim, or AMS Designer).
• Verify digital control loops.
• Create test benches for key performance metrics: transient response (load steps), loop stability, efficiency, ripple, over-current / over-voltage protection, and startup/shutdown sequences.
• Run regressions across PVT corners, Monte-Carlo analysis, and corner-case scenarios.
• Debug mixed-signal issues at both transistor-level and behavioral-level.
• Collaborate closely with analog designers, digital designers, and system engineers to close verification coverage.
• Develop automated verification scripts and improve verification methodology for faster turnaround.
• Support post-silicon validation by correlating simulation results with lab measurements.

• 5+ years hands-on experience in mixed-signal verification of power management ICs or analog/mixed-signal SoCs.
• Strong proficiency in mixed-signal simulation flows:
  Real Number Modeling (RNM) and Verilog-A behavioral modeling.
• Proficiency in analog-digital co-simulation (AMS, VCS + Spectre, Xcelium).
• Solid understanding of power converter topologies (buck, multi-phase, 3-level buck, switched-capacitor converters).
• Good knowledge of digital control concepts for power converters (PID controllers, DPWM, digital feedback loops).
• Experience with MATLAB/Simulink for system-level modeling and testbench reference generation.
• Proficiency in System Verilog and UVM for digital/mixed-signal test benches.
• Familiarity with Cadence Virtuoso, Spectre, or Synopsys Custom Sim for analog simulation.
• Understanding of analog non-idealities (quantization effects, loop delay, sensor offsets, PDN resonances, inductor non-linearities).
• BSEE / MSEE with 8+ years relevant experience.

• Experience verifying high-frequency IVRs, PoL regulators, or high-current power delivery systems.
• Experience with SIMPLIS, PLECS, or Simulink for system-level power electronics validation.
• Familiarity with digital PID controller verification and fixed-point arithmetic effects.
• Exposure to advanced packaging and on-die inductor modeling.
• Scripting skills in Python, Perl, or Tcl for automation.