Physical Design Implementation and STA Lead

About Altera

At Altera™, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.

We are seeking an experienced Physical Design Implementation & Static Timing Analysis (STA) Lead to play a key technical role in delivering high‑quality physical implementation and timing closure for next‑generation FPGA SoCs. In this role, you will lead physical design implementation and static timing analysis activities for complex blocks and SoC subsystems, driving implementation from floor planning through final timing closure while partnering closely with RTL, architecture, DFT, CAD, and signoff teams.

This is a highly technical individual contributor role with project leadership responsibilities. You will provide technical guidance to engineers across implementation and timing closure activities while helping improve methodologies and evaluating emerging ML/AI‑assisted physical design technologies.

• Lead block‑level physical implementation including synthesis, floor planning, place‑and‑route, clock tree synthesis (CTS), optimization, and ECO closure.
• Support SoC‑level physical implementation and collaborate on floor planning, partitioning, and integration strategies.
• Develop and maintain implementation constraints (SDC and UPF) to meet timing, power, and area (PPA) goals.
• Partner with RTL, DFT, CAD, packaging, and library teams to resolve implementation issues throughout the design cycle.
• Drive implementation convergence across timing, power, congestion, and routability objectives.
• Contribute to methodology improvements and implementation best practices.
• Perform static timing analysis (STA) using Synopsys Prime Time or equivalent STA tools; identify and resolve setup, hold, recovery, removal, SI/crosstalk, and clock‑related timing violations.
• Drive timing‑driven ECO implementation in collaboration with RTL and physical design teams.
• Develop timing constraints and validate timing exceptions to ensure robust signoff quality.
• Partner with library, CAD, and methodology teams to improve timing closure efficiency.
• Execute signoff activities including IR drop, electromigration (EM), DRC, LVS, antenna, and physical verification.
• Analyze congestion, routing quality, clock quality, and PPA tradeoffs.
• Support implementation planning to achieve project schedules and tapeout milestones.
• Utilize ML/AI‑assisted implementation technologies, develop Tcl and Python automation to streamline workflows, collaborate with CAD teams on AI‑assisted optimization methodologies, and analyze implementation metrics to identify optimization opportunities.
• Provide technical leadership for physical implementation and STA activities across multiple projects; mentor junior and mid‑level engineers, participate in design and timing reviews, contribute to reusable methodologies, automation, and engineering best practices.

Minimum Qualifications:

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related discipline with 7+ years of industry experience in physical design, implementation, or static timing analysis.
• 7+ years of experience in physical design, implementation, or SoC backend development for advanced semiconductor products.
• 5+ years of experience performing block‑level physical implementation (synthesis, floor planning, place‑and‑route, CTS, optimization, and ECO closure).
• 3+ years of experience performing static timing analysis using Synopsys Prime Time or equivalent STA tools, including multi‑mode multi‑corner (MMMC) timing analysis.

Preferred Qualifications:

• Master’s degree in Electrical Engineering, Computer Engineering, or a related discipline.
• 10+ years of experience in…