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Senior FPGA Verification Engineer - SystemVerilog & UVM
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-07-21
Listing for:
Teradyne
Full Time
position Listed on 2026-07-21
Job specializations:
-
Engineering
Test Engineer, Hardware Engineer
Job Description & How to Apply Below
Teradyne is seeking a Digital Functional Verification Engineer to drive planning, strategy, and execution of challenging FPGA verification projects. You will work under the supervision of a Verification Lead, interfacing with Hardware, Software, and Applications teams to ensure robust designs.
The role requires a strong background in System Verilog/UVM, verification planning, and Xcelium/Simvision tooling, with experience in standard protocols and IP integration.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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