IC Package Design Engineer

Meet the Team

The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow.

Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.

In this role, you will contribute to the development of complex ASIC package designs from early planning and exploration through implementation and tapeout. You will collaborate across package design, layout, SI/PI, and silicon teams to help deliver high‑speed, robust, and manufacturable package solutions.

You will participate in package architecture activities, design tradeoff discussions, and technical problem solving while growing your expertise in advanced packaging technologies and system‑level integration. This role provides an opportunity to work on some of the most advanced networking silicon products in the industry within a highly collaborative engineering environment.

• Contribute to package design activities including planning, floor planning, pinout optimization, stack‑up definition, and high‑speed routing support.
• Collaborate with SI/PI, silicon floor planning, layout, and manufacturing teams to ensure high‑quality package solutions.
• Support package implementation activities and work closely with layout editors to ensure alignment between design intent and physical implementation.
• Participate in technical investigations, design reviews, and tradeoff discussions involving performance, manufacturability, and schedule considerations.
• Assist in developing and improving package design methodologies, flows, and best practices.
• Contribute to debugging, issue resolution, and package bring‑up activities as needed.
• Work with package leads and senior engineers on complex package programs and progressively take ownership of larger design scopes.

• Bachelor’s with 5+ years of experience or Master’s degree with 3+ years of experience in Electrical Engineering or a related field.
• Experience in hardware, package, PCB, or high‑speed design engineering.
• Experience of high‑speed signaling, power delivery, and system‑level hardware concepts.
• Prior experience with industry‑standard EDA tools for package or PCB design.

• Experience in ASIC package design, PCB design, or related high‑speed hardware development.
• Experience with SI/PI concepts and collaboration with cross‑functional engineering teams.
• Experience with advanced packaging technologies, interposers, or multi‑die systems is an advantage.
• Experience with scripting languages such as (Python, Perl, TCL, or shell)

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

The starting salary range posted for this position is $ to $ and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.

Individual pay is…