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Senior FPGA DDR & IO Subsystem Architect
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-07-24
Listing for:
Dormont Manufacturing Co
Full Time
position Listed on 2026-07-24
Job specializations:
-
Engineering
Hardware Engineer, Test Engineer, Electronics Engineer -
Design & Architecture
Job Description & How to Apply Below
Altera is seeking an FPGA DDR and IO Subsystem Architect to define the architecture for high‑speed external memory and general IO subsystems across its FPGA product portfolio. This is a high‑visibility technical leadership role requiring deep expertise in DDR and high‑speed IO standards.
You will drive specifications, micro‑architecture, and lifecycle from concept to silicon bring‑up, collaborating with circuit design, PHY, packaging, verification, and software teams to deliver differentiated,
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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