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Senior Physical Design Engineer, SoC & PnR Expert
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-07-26
Listing for:
Fortell
Full Time
position Listed on 2026-07-26
Job specializations:
-
Engineering
Hardware Engineer, Electronics Engineer
Job Description & How to Apply Below
Fortell in California is seeking an experienced ASIC Physical Design Engineer to drive chip implementation from synthesis through signoff, partnering with architects, RTL designers, and DFT engineers. You will ensure power-aware convergence, meet strict schedules, and lead verification signoffs across partitions.
This role requires 7+ years in physical design, fluency with Innovus/Tempus/Quantus, and strong TCL scripting to optimize flows and reduce risk across SoC implementations.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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