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Design Verification Lead – PCIe/CXL IP, AI-Driven QA
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-07-27
Listing for:
AMD
Full Time
position Listed on 2026-07-27
Job specializations:
-
Engineering
Test Engineer, Hardware Engineer
Job Description & How to Apply Below
AMD in San Jose, CA is seeking a Design Verification Engineer Lead to advance FPGA/ASIC IP verification. You will work across architecture, IP design, physical design and firmware teams to ensure first-pass silicon success for high-speed IP solutions.
You bring deep UVM-based verification expertise, System Verilog and Python scripting, plus leadership experience mentoring distributed teams. This role emphasizes collaboration and technical excellence.
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