Electro-Optical Interconnect Packaging Development Hardware Engineer; Onsite

The application window is expected to close on: 09/30/2026

Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received

This position requires that you live within commuting distance of our San Jose, CA office and commute to the office 5 days per week.

The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We re a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow.

Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.

Cisco Silicon One (#Cisco Silicon One ) is a business organization with a long track record of building complex and high-performance Silicon ASICs. Our silicon devices drive the world’s most complex networks and carry over 90% of IP traffic. Cisco Silicon One is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio.

We are a highly specialized ASIC team with experts in all aspects of advanced IC package design and heterogeneous system integration. Our substrates use the latest 2.5D fanout technologies for large-scale integration, using the latest signaling and data transfer technologies. Come join us and take part in shaping Cisco s ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry!

As an Interconnect Packaging Development Engineer within the Silicon Core team, you will operate at the intersection of advanced packaging technology and strategic execution. You will be a key member of the platform development team responsible for designing, qualifying, validating, and debugging critical packaging technology building blocks, processes, and tools that support Cisco s cutting-edge Silicon One ASIC roadmaps.

In this highly collaborative role, you will partner with design engineering, operations, and supply chain teams to innovate next-generation technologies, including co-packaged optics and co-packaged copper. You will also engage directly with external OSATs, Fabs, contract manufacturers, and key suppliers to drive validation and problem-solving efforts.

• SI/PI Simulation & Analysis:
  Perform comprehensive Signal and Power Integrity (SI/PI) analysis and modeling using simulation tools including Ansys HFSS, Siwave, Q3D, and Keysight Pathwave ADS.
• Test Vehicle Definition:
  Define and specify advanced IC packaging test vehicles designed to provide empirically derived data for SI/PI tool verification.
• Model-to-Measurement Correlation:
  Provide rigorous model verification by synchronizing simulation models with physical, measured data to ensure high-fidelity predictive modeling.
• Thermal & Material Characterization:
  Conduct thermal analysis using tools like TMA, DMA, TGA, or DSC to evaluate laminate properties (e.g., Tg, CTE, out gassing),
• Dielectric Modeling:
  Perform Fabry Perot dielectric and Copper material characterization, matching empirical measured data to simulation. Generate and deliver frequency-dependent IC-packaging dielectric material models over temperature for use in simulation tools.
• Reliability & Material
  
  Qualification:
  
  Conduct hands-on reliability and material qualification testing to proactively identify and mitigate risks, resolving complex packaging issues.
• Failure Analysis (FA):
  Support quality investigations by performing root-cause failure analysis, executing material cross-sectioning, vacuum potting, polishing, and SEM/EDS imaging.
• On-the-Fly Prototyping:
  Utilize 3D CAD (Autodesk Fusion), 3D printing, and basic…