Physical Design Engineering, VP New United States

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.

The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at  .

Astera Labs is seeking a VP
of Physical Design to lead our critical full-chip physical design efforts for next-generation switching products featuring UCIe andUALinktechnologies. This strategic leadership role will drive the physical implementation ofhighly complex, multi-diechipletarchitectures that are essential to enabling rack-scale AI infrastructure. As AVP, you will scale and mentor a growing team of physical design engineers whileestablishingthe methodologies and flowsrequiredto deliver multiple high-performancetapeoutsin advanced process nodes.

This role sits at the intersection of cutting-edge connectivity technology and semiconductor execution excellence. You will partner closely with architecture, digital design, packaging, and silicon engineering teams to ensure our switching solutions meet the aggressive performance, power, and area targets demanded by hyperscale AI data centers. Yourexpertisein interposer design, die-to-die interfaces, advanced packaging, and timing closure will be critical as Astera Labs continues to push the boundaries of AI connectivity with PCIe Gen 6/7 andUALinktechnologies.

• Lead end-to-end physical design execution for complex multi-die switching products with UCIe andUALinkconnectivity
• Drive chip-levelfloorplanning, power planning, placement, routing, and timing closure for advanced node designs
• Establish physical design methodologies and best practices for interposer-basedchipletarchitectures and die-to-die interfaces
• Own physical design quality metrics including timing, power, area, and manufacturability across multiple concurrent projects
• Scale and develop a world-class physical design organization to support aggressive product roadmap
• Manage and mentor Directors, Managers, and senior engineers across the physical design team
• Foster a culture of technical excellence, innovation, and collaboration
• Partner with HR and recruiting to attract top physical design talent

• Partner with architecture and digital design teams to influence RTL for physical implementation success
• Collaborate with packaging engineering on advanced 2.5D/3D integration strategies and interposer design
• Work closely with silicon engineering and DFT teams to ensure robust designs throughtapeoutand bring-up
• Drive resolution of critical timing, power, and signal integrity challenges in high-speed Ser Des and switching fabrics

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
• 15+ years of experience in physical design and implementation of complex SoCs or ASICs
• Proven track record leading physical design teams and delivering multiple successfultapeoutsin advanced process nodes (7nm or below)
• Strong understanding of advanced packaging technologies including 2.5D and 3D integration
• Expert-level knowledge of physical design flows, timing closure, power optimization, and signoff methodologies
• Experience…