Interface IP Design Verification Engineer (PCIe/Ethernet
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-07-31
Listing for:
The Consensus
Full Time
position Listed on 2026-07-31
Job specializations:
-
Engineering
Test Engineer, Hardware Engineer, Electronics Engineer, Validation Engineer
Job Description & How to Apply Below
Etched is seeking a Design Verification Engineer for the Interface IP DV team. You will validate the architecture requirements across IP subsystems and interfaces, ensuring correctness and performance from hardware to software.
The role demands creativity and deep technical ability to tackle challenging verification tasks. You will own end-to-end verification for IP subsystems, work with vendor IP configurations, and develop scalable test benches using System Verilog/UVM.
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