Principal Engineer, Signal-Integrity and Power-Integrity

Job Title:
Principal Engineer, Signal-Integrity and Power-Integrity
Office

Location:

San Jose, CA
Work Model:
Onsite

About SK hynix America

At SK hynix America, we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a global leader in DRAM and NAND flash technologies, we drive the evolution of advancing mobile technology, empowering cloud computing, and pioneering future technologies. Our cutting-edge memory technologies are essential in today's most advanced electronic devices and IT infrastructure, enabling enhanced performance and user experiences across the digital landscape.
We're looking for innovative minds to join our mission of shaping the future of technology. At SK hynix America, you'll be part of a team that's pioneering breakthrough memory solutions while maintaining a strong commitment to sustainability. We're not just adapting to technological change – we're driving it, with significant investments in artificial intelligence, machine learning, and eco-friendly solutions and operational practices.

As we continue to expand our market presence and push the boundaries of what's possible in semiconductor technology, we invite you to be part of our journey to creating the next generation of memory solutions that will define the future of computing.

Job Summary:

SK hynix America is seeking a Principal Engineer to lead the Signal‑Integrity and Power‑Integrity (SIPI) strategy for next‑generation advanced packaging technologies. In this role, you will lead the design, analysis, and validation of next generation advanced packaging solutions for HBM and beyond HBM such as logic‑memory integration. The position requires deep technical expertise in high‑speed interface design, collaboration with global R&D teams, and contributions to industry standards for advanced packaging.

Responsibilities:

• Strategic Leadership:
  Define and own the SIPI roadmap for advanced PKG families, aligning technical direction with product and business goals.
• Architecture & Design:
  Lead the creation of high‑performance SiP architectures (HBM, interposer, 3D stacks) and validate power‑delivery and signal‑integrity across the full stack—from silicon to substrate.
• Methodology Development:
  Invent and propagate best‑practice SIPI methodologies, including electromagnetic extraction, multi‑port S‑parameter modeling, and power‑network analysis for complex packaging environments.
• Technical Ownership:
  Oversee the end‑to‑end design flow (package definition, simulation, layout sign‑off, tape‑out) and drive continuous improvement of tools, scripts, and automation.
• Mentorship & Talent Development:
  Coach senior and junior engineers, fostering expertise in SIPI analysis, tool usage, and design verification; champion knowledge‑sharing across global teams.
• Risk Management & Sign‑off:
  Conduct comprehensive risk assessments, lead design reviews, and deliver final SIPI sign‑off packages that meet performance, reliability, and schedule targets.

Qualifications:

• Education:
  
  Ph.D. in Electrical Engineering, or a related field (or Master’s degree with 5+ years of relevant industry experience).
• Experience:
  
  ≥5years of hands‑on SIPI engineering in advanced semiconductor packaging.
• Technical Expertise:
  Deep knowledge of 2.5D/3D package architectures, HBM, interposer, TSV, high‑speed I/O standards, and power‑delivery networks. Proven proficiency with SIPI simulation tools (e.g., Ansys SIwave/Red Hawk, Cadence Sigrity).
• Design Flow Mastery:
  Strong background in electromagnetic extraction, multi‑port S‑parameter analysis, power‑network optimization, and tape‑out sign‑off processes for complex packages.
• Leadership
  
  Skills:
  
  Demonstrated ability to influence multi‑disciplinary teams, drive technical decisions, and mentor senior engineers.
• Communication:
  Excellent verbal and written communication skills; ability to present complex technical concepts to both engineering and executive audiences.

Preferred Qualifications:

• Hands‑on experience with 2.5D/3D packaging for HBM, interposers, or GPU‑memory integration.
• Expertise in power integrity (PI) for 3D‑stacked memory systems, including PDN…