Senior Physical Design Engineer​/Lead

Physical Design Engineer

At Altera™, our independence as the world's largest pure-play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry-leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.

About the Role

As a Physical Design Engineer at Altera, you will play a critical role in our backend implementation flow—from RTL/netlist through to GDSII/tape-out for FPGA/SoC devices. You will interface with architecture, logic design, DFT, CAD/EDA, and manufacturing teams to achieve our performance/power/area (PPA) goals, with particular emphasis on programmable logic structures, block and full-chip integration, and the unique demands of FPGA technologies (e.g., configurable logic blocks, routing fabrics, I/O rings, on-chip power domains).

Key Responsibilities

• Lead and execute physical design implementation tasks (floor planning, power planning, placement, clock tree synthesis (CTS), routing, engineering change orders (ECO), extraction, sign-off preparation) from netlist → GDSII.
• Apply PPA optimization techniques (performance / timing closure, power reduction, area efficiency) across blocks or full-chip hierarchies.
• Collaborate with front-end design, architecture, CAD/EDA tool teams to ensure physical design constraints, timing budgets, power budgets and DFT Insertions are met.
• Develop and improve physical design flows, methodologies, scripts and automation frameworks (TCL, Python, Perl) to accelerate turnaround, improve QoR and reduce manual intervention.
• Participate in timing, power, EM/IR integrity, signal/power noise, DRC/LVS/ERC verification and sign-off readiness.
• Integrate FPGA-specific physical design aspects: configurable logic block placement, fabric routing, I/O ring optimization, power domains for programmable regulation, and yield optimization.
• Work closely with manufacturing and packaging partners to ensure implementation is manufacturable (DFM/DFY), meets yield targets and meets high-volume production requirements.
• Debug physical design issues, interact with CAD tool vendors and internal tool teams to drive tool enhancements or workarounds.
• Mentor and collaborate with junior engineers; contribute to reviews, documentation of flows, and continuous process improvement.

Salary Range

The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.

$149,100 - $215,000 USD

We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical discipline with 10+ years of industry experience in physical design, physical implementation, or SoC backend design, including the following:
• 10+ years of hands-on experience in digital ASIC and/or SoC physical design, including synthesis, floor planning, place-and-route, clock tree synthesis (CTS), routing, engineering change order (ECO) implementation, and signoff.
• 8+ years of experience using industry-standard EDA implementation and signoff tools such as Synopsys IC Compiler II, Synopsys Fusion Compiler, Cadence Innovus, Cadence Encounter, Synopsys Prime Time, Synopsys StarRC (STAR-RCX), Mentor Calibre, or equivalent tools.
• 5+ years of scripting and automation experience using Tcl for physical design flow development and automation.
• 2+ years of experience using Python, Perl, Shell, or similar programming languages to improve physical design productivity and workflow automation.
• 8+ years of experience with physical…