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Tech Lead - AI Connectivity Silicon Design

Job in San Jose, Santa Clara County, California, 95199, USA
Listing for: Astera Labs
Full Time position
Listed on 2026-08-06
Job specializations:
  • Engineering
    Hardware Engineer, Electronics Engineer
  • Design & Architecture
Salary/Wage Range or Industry Benchmark: 133000 - 185000 USD Yearly USD 133000.00 185000.00 YEAR
Job Description & How to Apply Below

Astera Labs is seeking a Tech Lead Design Engineer to architect and deliver connectivity silicon powering AI clusters. You will own RTL design for assigned blocks from microarchitecture through synthesis, and drive high-quality design flows.

This high-impact role requires collaboration with architecture, verification, DFT, and physical design to move features from spec to silicon and ensure tapeout readiness.

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