CAD Timing Engineer - Gate-Level Flows & Methodologies
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-08-07
Listing for:
Apple Inc.
Full Time
position Listed on 2026-08-07
Job specializations:
-
Engineering
Electronics Engineer, Engineering Design & Technologists
Job Description & How to Apply Below
Apple Inc. is seeking a CAD Engineer focused on Timing for Gate-Level Flows & Methodologies in San Jose, CA. You will contribute to timing analysis, create and refine flows, and partner with design teams to drive first-time silicon success.
In this role you will develop and maintain gate-level STA flows, debug issues related to constraints and scripts, and work with EDA vendors to adopt new capabilities for performance and productivity gains. A BS degree and 3 years’ experience are required.
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