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Silicon RTL Tech Lead for AI Interconnect
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-08-07
Listing for:
Astera Labs
Full Time
position Listed on 2026-08-07
Job specializations:
-
Engineering
Hardware Engineer, Systems Engineer, Test Engineer
Job Description & How to Apply Below
Astera Labs is seeking a Tech Lead Design Engineer to own RTL design for critical connectivity blocks powering AI infrastructure. You will drive from microarchitecture to tapeout, delivering synthesizable Verilog/System Verilog with emphasis on timing, CDC, and low-power strategies.
You will collaborate across architecture, verification, DFT, and physical design to ensure robust, scalable silicon while mentoring junior engineers and contributing to design methodology.
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