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Lead RTL Design Engineer: Power-Efficient Edge SoC

Job in San Jose, Santa Clara County, California, 95199, USA
Listing for: Efficient Computer
Full Time position
Listed on 2026-08-09
Job specializations:
  • Engineering
    Systems Engineer, Electronics Engineer, Hardware Engineer
Salary/Wage Range or Industry Benchmark: 160000 - 250000 USD Yearly USD 160000.00 250000.00 YEAR
Job Description & How to Apply Below
Efficient Computer is seeking a Lead RTL Design Engineer to own microarchitecture definition and RTL design across various systems in Pittsburgh. The role involves collaborating with teams to deliver a power-efficient SoC and provides a unique opportunity to influence product development. Candidates should have 8+ years in RTL design and strong knowledge of System Verilog, parallel execution models, and low-power design techniques.

Competitive salary ranges from $160K to $250K, along with equity and benefits.
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