Director, Physical Design (Silicon One

The application window is expected to close on: 08/10/2026

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. With 2,100 employees across 16 countries, we design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio.

Come join us and take part in shaping Cisco's revolutionary solutions by designing, developing and testing some of the most complex ASICs being developed in the industry.

• Strategic Execution:
  
  Develop and manage SoC execution schedules, tracking critical milestones and communicating project status and risks to senior management.
• PPA Optimization:
  
  Own the optimization of floor-plans, area, and interconnects during early chip development to meet stringent Power, Performance, and Area (PPA) goals.
• Technical Leadership:
  
  Drive SoC Physical Design implementation in advanced process nodes, leading a world-class team of Physical Design, Circuit Design, DFT, and integration engineers.
• Cross-Functional Collaboration:
  
  Maintain close interaction with global teams across RTL, NPI, Packaging, DFT, and Architecture to identify improvement opportunities and review design constraints.
• Infrastructure
  
  Innovation:
  
  Build and oversee the development of automation utilities and infrastructure to optimize chip area, improve quality, and accelerate execution speed.
• Quality Assurance:
  
  Conduct periodic design reviews with deep technical dives—including EMIR analysis and timing signoff closure to ensure high-quality work and schedule alignment.
• Team Growth:
  
  Build and scale a high-performing team of passionate leaders as the organization grows.
• Flow Mastery:
  
  Apply an expert understanding of both Front-End (FE) and Back-End (BE) ASIC flows to drive design methodology from concept to release.

• Bachelor's Degree in a technical field, preferably engineering and 15+ years of experience in the hardware industry with proven management experience leading SoC and Physical Design teams.
• Demonstrable experience leading and managing large ASIC developments in advanced process nodes.
• Prior experience in developing Physical Design execution schedules and tracking milestones.
• Demonstrable hand-on experience in ASIC design from concept to release.

• Knowledge of industry-standard PnR and Sign-off tools and their capabilities.
• Hands-on experience in block-level synthesis, place and route, timing closure, and advanced power/integrity analysis.
• Proficiency in scripting languages such as Tcl and Python.
• Expertise in managing Static Timing Analysis (STA), timing closure, and design constraints.
• Self-motivated with the ability to work effectively in a highly cross-functional, global team environment.

At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.