SMTS, Design Engineer

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

As a Senior Member of Technical Staff (SMTS) Design Engineer in Micron's NVEG organization, you will serve as a principal technical authority driving the architecture and implementation of innovative high-speed datapath circuits for next-generation NAND flash memory! In this role, you will own the design, layout, and optimization of datapath circuits targeting industry-leading data rates (10+Gbps) and power efficiency!

Your deep expertise in system-level modeling, timing budgets, and SI/PI analysis will enable pathfinding for next-generation high-speed IO architectures. You will evaluate emerging topologies and interface standards, establish feasibility through quantitative analysis, and drive architectural decisions from exploration through silicon validation. Leading multi-functional task forces with TD, PE, and SIRD teams, you will resolve sophisticated SI/PI challenges and ensure first-silicon success.

Your technical leadership will shape Micron's IO roadmap while mentoring engineers in sophisticated design techniques.

Design and verify sophisticated IO/datapath blocks (input receiver, serializer/deserializer, clock distribution, equalizer, ZQ calibration, ONFI training, wave pipelines) while driving architectural decisions to meet aggressive performance targets. Evaluate trade-offs between circuit topologies, power, area, and speed to establish optimal design directions. Conduct layout reviews, model parasitics, and optimize circuit performance, area efficiency, and power consumption.

Lead early-stage exploration of next-generation IO architectures through system-level modeling, timing budget development, and signal/power integrity analysis. Model transmission line effects, power delivery networks, and crosstalk to establish feasibility boundaries and define design specifications that balance performance targets with manufacturing constraints.

Define block interface specifications and negotiate technical trade-offs with integration, TD, and SIRD teams. Align with Applications Engineering on feasibility of new customer requirements, quantifying design margin and implementation risk.

Partner with Product Engineering to design silicon experiments, lead root-cause analysis of performance issues, and correlate measurements to models. Propose circuit-level or architectural fixes that improve yield and close performance gaps.

Establish design methodologies and standard processes. Present technical findings to expert review panels. Actively mentor engineers in sophisticated circuit techniques, system-level thinking, and SI/PI analysis.

• Bachelor of Science or Master of Science in Electrical Engineering, or a related filed with 12+ years of relevant IC design experience, including multiple successful tape-outs of high-speed IO circuits.
• Demonstrated technical authority in high-speed IO circuit design with deep understanding of signal integrity, power integrity, and circuit performance optimization across PVT corners.
• Track record of technical leadership in sophisticated IC development, including driving architectural decisions, leading technical task forces, and influencing multi-functional teams.
• Experience with physical design flows, layout optimization, and parasitic extraction for performance-critical circuits.
• Proven expertise in system-level modeling, timing budget development, and SI/PI analysis for multi-Gbps interfaces, including transmission line modeling, power delivery network design, and crosstalk mitigation. Ability to establish feasibility boundaries and drive architectural trade-offs.
• Strong project management skills with the ability to lead sophisticated design initiatives and effectively…