Physical Design Engineer

About Altera

At Altera, our independence as the world's largest pure-play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry-leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely-empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.

At Altera, our independence as the world's largest pure-play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry-leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely-empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.

We are seeking a Physical Design Engineer to join our Silicon Design Automation & Implementation organization. In this role, you will contribute to the implementation of custom IP and SoC designs from RTL through GDSII, supporting timing closure, power optimization, physical verification, and design signoff for leading-edge semiconductor products. You will work closely with architecture, RTL, DFT, synthesis, verification, and methodology teams to help deliver high-quality silicon for next-generation FPGA technologies.

• Perform block-level physical design implementation of custom IP and SoC designs from RTL through GDSII, supporting the delivery of manufacturing-ready design databases.
• Execute and support stages of the physical design flow, including synthesis, floor planning, power planning, place and route, clock tree synthesis (CTS), timing analysis, and physical optimization.
• Perform static timing analysis (STA) and help resolve setup, hold, signal integrity, and other timing violations to achieve design closure.
• Support the development and optimization of clock distribution networks, power distribution networks, and multiple power domain implementations to meet performance, power, and reliability targets.
• Participate in physical verification and signoff activities, including formal equivalence checking (LEC), static timing analysis, power integrity, IR drop, electromigration (EM), layout verification, electrical rule checking (ERC), design rule checking (DRC), layout versus schematic (LVS), and structural verification.
• Analyze physical design results, identify root causes of implementation issues, and work with senior engineers and cross-functional teams to implement corrective actions.
• Optimize physical implementations to improve product-level metrics including performance, power consumption, frequency, area (PPA), manufacturability, and reliability.
• Collaborate closely with RTL, Logic Design, DFT, CAD, Architecture, Verification, and Product Engineering teams throughout the design cycle.
• Support Design-for-Test (DFT) integration and implementation throughout physical design and signoff.
• Support physical design convergence across multiple design iterations while balancing timing, power, congestion, and area tradeoffs.
• Contribute to the development, enhancement, and automation of physical design methodologies, flows, and infrastructure.
• Apply physical implementation best practices and contribute to continuous improvements in design quality and…