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RTL Design Intern - Verilog & ASIC Microarchitecture
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-08-22
Listing for:
Etched.ai, Inc.
Apprenticeship/Internship
position Listed on 2026-08-22
Job specializations:
-
Engineering
Hardware Engineer
Job Description & How to Apply Below
Etched.ai, Inc. in San Jose seeks an RTL Intern to design microarchitecture and implement logic in Verilog. You will work on cutting-edge machine learning architectures and contribute through the full design cycle from discussions to synthesis.
The ideal candidate has relevant educational progress in engineering and familiarity with high-speed digital logic and ASIC design. This is a 12-week paid internship with generous housing support, mentorship, and meals provided.
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