Summer 2024 - Design DFT​/DV Engineer Intern (5305

You will be part of the DFT and verification team responsible for all logic test chips designed at TSMC for yield learning in advanced process nodes as well as advanced packaging. You will be working on solving challenges associated with test chips in advanced process nodes.

This Internship Program is open to students currently enrolled in a degree-seeking University that are graduating in the year 2024 with a MS Degree. The Summer 2024 Internship will begin in May 2024 and continue through at least August 2024.

Responsibilities

• Perform block/top-level DFT/DV pattern simulation and generate TCL/Verilog monitors to generate run-time information during simulation to track simulation progress
• Insert pre-defined defects including static/dynamic defects/fail, and run simulation to collect fail logs to automatically identify the source of failure through clustering
• Build ATPG and test model (STIL/CTL/BSDL/WGL) explorer to modify and update files according to design changes
• Utilize machine learning and data mining techniques for simulation failure diagnosis in advanced process nodes

Minimum Qualifications

• Currently pursuing M.S in Electrical or Computer engineering and graduating in 2024
• Strong problem solving and programming skills (Verilog/Python/TCL)
• Experience in using Python to build machine learning models
• Fundamental knowledge of DFT techniques include ATPG, simulation, logic diagnosis, and Scan compression

Preferred Qualifications

• Experience with Synopsys DFT Complier, Tetramax and VCS is a plus

Company Description

As a trusted technology and capacity provider, TSMC is driven by the desire to be:

• The world’s leading dedicated semiconductor foundry
• The technology leader with a strong reputation for manufacturing excellence
• Advancing semiconductor manufacturing innovations to enable the future of technology

TSMC pioneered the pure-play foundry business model when it was founded in 1987 and has been the world’s leading dedicated semiconductor foundry ever since. The Company supports a thriving ecosystem of global customers and partners with the industry’s leading process technologies and a portfolio of design enablement solutions to unleash innovation for the global semiconductor industry. With global operations spanning Asia, Europe, and North America, TSMC serves as a committed corporate citizen around the world.

In North America, TSMC has a strong sales and service organization that works with customers by helping them achieve silicon success with cutting-edge technologies and manufacturing excellence. The Company has continued to accelerate its R&D investment and staffing in recent years and is expanding its manufacturing footprint to support customer innovation with 3D IC technologies and optimal manufacturing capacity.

Diversity statement

TSMC Technology, Inc. is committed to employing a diverse workforce and provides Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, or any other characteristic protected by applicable law.

TSMC is an equal opportunity employer prizing diversity and inclusion. We are committed to treating all employees and applicants for employment with respect and dignity. If you require reasonable accommodation due to a disability during the application or the recruiting process, please feel free to notify us at  TSMC confirms to all applicants its commitment to meet TSMC’s obligations under applicable employment law.

Reasonable accommodations will be determined on a case-by-case basis.

Pay Transparency Statement

At the time of this posting, this role typically pays an hourly rate between $36.00 and $42.00 per hour. The range displayed reflects the minimum and maximum target for new hires. Actual pay may be more or less than the posted range. Factors that influence pay include the individual's skills, qualifications, education, experience and the position level and location.