Senior Hardware Design Engineer

The era of pervasive AI has arrived. In this era, organizations will use generative AI to unlock hidden value in their data, accelerate processes, reduce costs, drive efficiency and innovation to fundamentally transform their businesses and operations at scale.

Samba Nova Suite™ is the first full-stack, generative AI platform, from chip to model, optimized for enterprise and government organizations. Powered by the intelligent SN40L chip, the Samba Nova Suite is a fully integrated platform, delivered on-premises or in the cloud, combined with state-of-the‑art open‑source models that can be easily and securely fine‑tuned using customer data for greater accuracy. Once adapted with customer data, customers retain model ownership in perpetuity, so you can turn generative AI into one of their most valuable assets.

The hardware design team writes the RTL for Samba Nova's RDU, the processor behind our AI workload acceleration systems, covering the compute, memory, and networking subsystems. Engineers own specific blocks inside a larger subsystem, working alongside the principal engineers and architects who set its direction. A block stays with the engineer who wrote it through PPA closure, tapeout, and bring‑up, so you debug your own design in silicon.

Samba Nova Senior Hardware Design Engineers design component units of the Reconfigurable Dataflow Unit (RDU) ASICs deployed in our AI workload acceleration systems. You will work alongside principal engineers, architects, design verification engineers, and physical design engineers to implement innovative features in hardware that provide unique value to Samba Nova.

In this role you will take ownership of blocks within a larger subsystem — contributing sections of the microarchitecture specification, writing and debugging the RTL, and carrying your blocks through implementation, tapeout, and silicon bring‑up. You will grow your scope over time as you build depth in our architecture.

This role is onsite, based in either our San Jose, CA or Austin, TX office.

Some of your responsibilities will include...

• Work with principal engineers and architects to author sections of the microarchitecture specification for compute, memory, or networking subsystems.
• Code, integrate, and debug System Verilog RTL for assigned blocks through the chip implementation and production lifecycle.
• Meet Power, Performance, and Area (PPA) targets for your blocks using advanced digital design techniques for high-speed design.
• Partner with design verification and physical design engineers to converge on functionality, timing, and area.
• Implement System Verilog Assertions (SVA) and run lint, CDC, and LEC flows to check design intent and keep blocks clean.
• Participate in design reviews, presenting your design decisions and incorporating feedback.
  
  Support post-silicon bring‑up and debug for the blocks you own.
• Contribute to design flow improvements, including AI and automation in EDA tool methodologies.

• Master's degree in Computer Engineering or Electrical Engineering with 3–5 years of relevant experience, or Bachelor's degree with 5–7 years.
• Solid foundation in computer architecture and digital logic design.
• Strong System Verilog RTL design skills for high-speed, high-performance ASICs.
• Experience making design decisions that trade off Power, Performance, and area (PPA).
• Working knowledge of industry‑standard interconnects and protocols (e.g., AXI, PCIe, Ethernet, HBM/DDR).
• Experience with digital logic synthesis tools and Static Timing Analysis (STA).
• Proficiency with industry‑standard tools for linting, Clock Domain Crossing (CDC), and Logical Equivalence Checking (LEC).
• Experience implementing System Verilog Assertions…