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Lead DDR Validation Engineer: -Up & Automation
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-08-26
Listing for:
Cadence Design Systems
Full Time
position Listed on 2026-08-26
Job specializations:
-
Engineering
Validation Engineer, Test Engineer
Job Description & How to Apply Below
Cadence Design Systems is seeking a leader to drive electrical and functional validation for next-generation DDR interfaces (DDR5/LPDDR5/LPDDR6/HBM4/GDDR7). You will design innovative testing strategies, accelerate post-silicon bring-up, and transform data into insights through advanced analysis and visualization.
The role requires M.Tech with 4+ years or
B.Tech with 6+ years experience, with strong Python automation, debugging, and cross-team collaboration across locations.
Position Requirements
5+ Years
work experience
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