Senior RTL Engineer, IO Die and Interconnect IP

Please Note:

To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period.

Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future.

We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.

Location: Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

• Develop RTL (Verilog/System Verilog) for the IO die, integrating UCIe, PCIe, and other high-speed interconnect IP into a cohesive chiplet-based architecture.
• Integrate internal and third-party interconnect IP - UCIe, PCIe, CXL, die-to-die, and NoC - into the IO die, including configuration, glue logic, clock/reset, and interface bridging.
• Modify and customize PCIe and other interconnect IP as needed - controller, PIPE/PHY interface, and configuration logic - to meet die-level requirements and close functional gaps.
• Define and implement die-to-die and chiplet interfaces using UCIe, ensuring protocol compliance and interoperability across chiplets.
• Own the microarchitecture and RTL for IO subsystems such as PCIe/CXL controllers, UCIe adapters, and interconnect fabric bridges.
• Collaborate with verification engineers to develop test plans and debug functional issues at the IP, subsystem, and die level.
• Work with architecture, PHY/Ser Des, physical design, and software teams to close requirements across performance, power, area, and interoperability.
• Make design decisions out of a large design trade-off space across performance, power, latency, bandwidth, and cost.
• Develop and automate IP integration and RTL assembly flows using scripting and agentic AI tools and frameworks to improve turnaround time and quality of results.
• Communicate effectively with stakeholders, including users, partners, and management, to ensure that the die is delivered on time and within budget.
• Complete other responsibilities as assigned.

• Bachelor’s with 5+ years, or Master’s with 3+ years, or PhD's with 0+ years of industry experience.
• Strong background in microarchitecture and RTL design for complex SoC and die integration.
• 5+ years of experience in RTL development (Verilog/System Verilog) for high-speed interconnect and IO subsystems.
• Hands-on experience integrating and configuring interconnect IP such as PCIe, CXL, UCIe, and die-to-die interfaces.
• Experience modifying or customizing third-party interconnect IP (e.g., PCIe controller, PIPE, or PHY interface) to meet die-level requirements.
• Familiarity with UCIe and chiplet-based, multi-die architectures and die-to-die interconnect.
• Solid understanding of PCIe/CXL protocol stacks (transaction, data link, and physical layers) and the PIPE interface.
• Experience with SoC integration methodologies, IP packaging (e.g., IP-XACT), and on-chip interface protocols such as AXI, ACE, CHI, or APB.
• Proficiency in scripting (Tcl, Python, or Perl) for design integration and automation; familiarity with agentic AI tools and frameworks is a plus.
• Experience in AI/ML workloads.
• Strong analytical and problem-solving skills
• Excellent communication and interpersonal skills
• Ability to work independently and as part of a team
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change

#LI-VL1

The pay range below is for all roles at this level…