ASIC Packaging Engineer Intern — Design, Yield & Innovation
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-08-28
Listing for:
Advanced Micro Devices
Full Time, Apprenticeship/Internship
position Listed on 2026-08-28
Job specializations:
-
Engineering
Quality Engineering, Engineering Design & Technologists
Job Description & How to Apply Below
AMD invites motivated students for an ASIC Package Engineering internship/co-op in the San Jose/Santa Clara area. You will work 40 hours per week in a hybrid or onsite setting across the co-op/intern term, contributing to advanced packaging technologies and test vehicles.
You will gain hands-on experience in substrate, interposer, and bump design, design verification, and yield analysis while collaborating with seasoned engineers.
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