Design Verification Engineer

Arrow Electronics is seeking a Design Verification Engineer to join our Engineering & Design team in the Electronics industry. In this role, you will develop and execute verification plans for complex digital designs, create and maintain System Verilog/UVM test benches, and ensure functional correctness, performance, and reliability of cutting-edge electronic systems. You will analyze coverage, debug failures, and collaborate closely with design, FPGA/ASIC, and validation teams to drive first-pass success.

In our performance-driven, innovative, and collaborative culture, you'll solve complex technological challenges, contribute to customer success, and engage in continuous learning. This opportunity offers global exposure, cross-functional collaboration, and the chance to shape the future of technology across diverse industries.

Responsibilities

• Develop, document, and execute verification plans for complex digital and mixed-signal designs.
• Design, implement, and maintain System
• Verilog/UVM test benches and reusable verification components.
• Create constrained-random, directed, and regression test suites to ensure thorough functional coverage.
• Analyze and close code, functional, and assertion coverage metrics; identify and fill coverage gaps.
• Debug simulation failures, root-cause design issues, and collaborate with design teams on fixes.
• Integrate formal verification methods and tools where appropriate to enhance verification quality.
• Review specifications, architectures, and RTL to identify risks and verification requirements early.
• Collaborate with FPGA/ASIC, validation, and software teams to ensure end-to-end product quality.
• Document verification results, methodologies, and best practices for global engineering teams.
• Contribute to continuous improvement of verification flows, automation, and CI/CD integration.

Required Skills

• System
• Verilog for verification
• UVM (Universal Verification Methodology)
• Digital design and RTL (Verilog/VHDL) understanding
• Constrained-random stimulus generation
• Coverage-driven verification (functional/code/assertion)
• Simulation tools (e.g., Questa, VCS, Xcelium)
• Debug tools and waveform analysis
• Scripting (Python, Perl, or Tcl) for automation
• Formal verification tools and methodologies
• Version control and CI/CD (Git, Jenkins or similar)