ASIC DFT Emulation Technical Lead

ASIC DFT
- Emulation Technical Lead

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#Cisco Silicon One ) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio.

Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry.

As an ASIC DFT
- Emulation Technical Lead, you will play a critical role in driving the DFT emulation strategy for Silicon One. You'll architect state-of-the-art emulation environments, lead pre-silicon test plan execution, and validate complex scan, MBIST, and JTAG architectures on platforms like Palladium, Veloce, or Zebu. Partnering closely with front-end RTL, physical design, and ATPG teams, you will troubleshoot critical issues and ensure high-quality post-silicon pattern conversion.

Your technical leadership and cross-functional collaboration will guarantee seamless silicon bring-up and optimal test coverage across next-generation hardware platforms.

• Bachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of related experience
• Prior emulation experience on platforms such as Palladium, Veloce, or Zebu as well as experience with compilation and debug.
• Prior experience with Verilog and System Verilog.
• Prior experience with C/C++ and scripting skills with Tcl or Python/Perl.

• Prior experience defining DFT Emulation strategy.
• Prior experience with JTAG protocol, scan architecture, MBIST and boundary scan.
• UVM and advanced System Verilog knowledge.
• Post Silicon validation and/or debugging experience.

At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions.

Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

The starting salary range posted for this position is $ to $ and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits. Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below.

For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.

U.S. employees are offered benefits, subject to Cisco's plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.

U.S. employees are…