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Silicon Validation & Characterization Intern; Fall, SJ
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-09-02
Listing for:
Cadence
Apprenticeship/Internship
position Listed on 2026-09-02
Job specializations:
-
Engineering
Electronics Engineer, Test Engineer
Job Description & How to Apply Below
Cadence DDR IP group is seeking a Post-Silicon Validation Engineering Intern in San Jose. The role focuses on validating system-level and electrical performance of internal silicon test chips, with close collaboration across analog and digital teams to debug issues and deliver characterization reports.
Ideal candidates are pursuing a BS or MS in electrical engineering, with strong fundamentals in analog/digital electronics, RTL, and signal integrity.
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