Mixed-Signal Verification Engineer

Senior Mixed-Signal Verification Engineer

• Lead verification planning, testbench development, and coverage closure for complex mixed-signal semiconductor designs.
• Develop System Verilog-based behavioral models and verification environments for analog and digital interfaces.
• Perform simulation-based verification, functional correlation, and equivalence analysis across mixed-signal blocks.
• Partner with analog and digital design teams to debug issues and support pre-silicon verification and sign-off.
• Develop automation scripts and verification utilities to improve efficiency, regression coverage, and workflow scalability.
• Verify a range of analog and mixed-signal subsystems, including signal-processing, power, timing, and interface circuitry.
• Use industry-standard circuit simulators, HDL simulation environments, and scripting languages such as Python and Perl for verification and analysis.

• 5+ years of experience in mixed-signal IC verification or a closely related field.
• Strong understanding of analog/mixed-signal design concepts, System Verilog, SPICE-based simulation, and verification methodologies.
• Experience with behavioral modeling, simulation/debugging, coverage analysis, and verification automation.
• Strong analytical, communication, collaboration, and problem-solving skills.