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Principal DV Engineer: SerDes/PHY IP AI Systems
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-09-03
Listing for:
Astera Labs
Full Time
position Listed on 2026-09-03
Job specializations:
-
Engineering
Test Engineer, Hardware Engineer
Job Description & How to Apply Below
Astera Labs is seeking a Principal Design Verification Engineer to own functional verification of high-speed Ser Des/PHY IP. You will architect verification environments, drive coverage closure, and ensure first-pass silicon success across PCIe Gen 6/7, UALink, UCIe, and Ethernet interfaces.
You will collaborate with analog/mixed-signal designers, digital architects, and SoC teams to verify multi-Gbps Ser Des blocks and guide the DV team through tape-out readiness and post-silicon validation.
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