Principal Hardware Systems Architect-Compute Platforms

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Req
Region:
Americas
Country: USA
State/Province:
California
City:
San Jose

Celestica is seeking a Principal Hardware Systems Architect for Compute Platforms to provide senior technical leadership for the architecture and development of next-generation AI, accelerated computing, and high-performance data center platforms.

This role will lead compute-platform architecture spanning CPUs, GPUs and AI accelerators, memory, storage, PCIe/CXL, scale-up interconnects, and compute-node/tray architecture, while collaborating with peer domain architects and engineering leaders to define complete rack and multi-rack systems incorporating networking, power, thermal, mechanical, firmware, and system-management technologies.

This is a system and platform architecture role, not a processor or ASIC design role. The successful candidate will operate above the component level, translating customer requirements, workload needs, and technology roadmaps into scalable compute architectures.

A critical aspect of the position is understanding that next-generation AI infrastructure can no longer be optimized as independent compute, networking, power, and cooling subsystems. The Compute Architect will partner closely with Celestica's Network Architect and other domain experts to optimize the complete AI system from compute node through rack and multi-rack deployments.

Define architecture for next-generation AI, accelerated-compute, server, and high-performance computing platforms.

Own architectural definition of:

GPU and AI accelerator subsystems

Memory and HBM architectures

PCIe and CXL fabrics

Local storage and NVMe architectures

GPU/accelerator topology

Compute node and tray architecture

Establish compute-system requirements, interfaces, partitioning, and architectural tradeoffs.

Evaluate alternatives based on performance, bandwidth, latency, power, thermal density, reliability, cost, scalability, serviceability, and manufacturability.

Develop reusable compute-platform architectures and building blocks that can be leveraged across customers and programs.

Maintain deep technical understanding of evolving CPU, GPU, AI accelerator, memory, storage, and interconnect technologies.

Track and evaluate technology roadmaps from leading compute ecosystem suppliers including NVIDIA, AMD, Intel, ARM ecosystem companies, and emerging AI accelerator providers.

Understand emerging AI compute architectures and their implications for:

Memory bandwidth

Scale-up fabrics

Scale-out networking

Rack and cluster architecture

Lead architectural evaluation of scale-up technologies, including NVLink/NVSwitch-class technologies and emerging accelerator interconnects.

Partner with peer system architects to define integrated rack and multi-rack architectures spanning compute, networking, power, thermal, mechanical, firmware, and system-management domains.

Optimize architecture as a complete AI system rather than as independent compute or networking platforms.

Partner closely with the Network Architect to establish the interface between accelerator scale-up architectures and network scale-out architectures.

Jointly evaluate system-level architectural tradeoffs where compute and networking intersect, including:

Fabric bandwidth

Switch topology

Power consumption

Reliability

Cost

Scalability

Work with Power, Thermal, Mechanical, Reliability, Firmware, and Validation engineering teams to establish system-level requirements and interfaces.

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, Physics, or related technical field.

Typically 12+ years of relevant hardware and system-development experience, with significant experience in server, compute, AI, HPC, or data-center platforms.

Demonstrated experience defining or leading system-level architecture for complex compute platforms.

Strong knowledge of modern server architectures including x86 and/or ARM processors, GPUs/accelerators, DDR/HBM, PCIe, CXL, NVMe/storage, and high-speed interconnects.

Strong understanding of the relationships among compute, networking, memory, power, and thermal architecture.

Experience taking complex platforms from early architecture through development, validation, and production.

Ability to…