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Senior Principal Physical Design Engineer - On-Site SoC Signoff
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-09-04
Listing for:
Asteralabs
Full Time
position Listed on 2026-09-04
Job specializations:
-
Engineering
Hardware Engineer, Test Engineer, Electronics Engineer
Job Description & How to Apply Below
Astera Labs is seeking a Senior Principal STA Physical Design Engineer to own RTL-to-GDS flows and full-chip signoff for our connectivity ASIC portfolio. This on-site role requires collaboration with RTL, frontend, and verification teams to ensure robust convergence across complex SoCs.
Qualified candidates have 10+ years in PnR/sign-off, Cadence/Synopsys tool proficiency, and strong scripting (Tcl/Python/Perl). California on-site position with competitive USD salary.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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